The demand for urban transport: An application of discrete choice model for Cadiz

The study of the demand for transport has among others applications, the valuation of travel time saving that is a very important question in cost-benefit analysis, and to adopt transport policy tools. Since McFadden developed a discrete choice model for travel demand, it has usually been the application of this model to study the individual behaviour when he has to choice among transport modes. Citizens of big cities have to face traffic congestion; pollution, wasted time in travels and fuel, noise, stress and accidents are the costs imposed by congestion to society, elements that reduce the quality of life in cities. Public transport is a real alternative to private transport that is socially less expensive, for this reason this paper tries to forecast travel demand for public transport in Cadiz when travelling have to choice between public or private transport, using a discrete choice model. The results of this analysis (travel demand, value of time, elasticities) can be used to design transport policies that could reduce congestion.

Towards a Software Transactional Memory for heterogeneous CPU-GPU processors

The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip. Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes. However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism. Transactional Memory (TM) is an optimistic approach to implement mutual exclusion. With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses. TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors. In this paper we present APUTM, a software TM designed to work on heterogeneous APU processors. The design of APUTM focuses on minimizing the access to shared metadata in order to reduce the communication overhead via expensive platform atomics. The main objective of APUTM is to help us understand the tradeoffs of implementing a sofware TM on an heterogeneous CPU-GPU platform and to identify the key aspects to be considered in each device. In our experiments, we compare the adaptability of APUTM to execute in one of the devices (CPU or GPU) or in both of them simultaneously. These experiments show that APUTM is able to outperform sequential execution of the applications.This work has been supported by projects TIN2013-42253-P and TIN2016-80920-R, from the Spanish Government, P11-TIC8144 and P12- TIC1470, from Junta de Andalucía, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Time Series Heterogeneous Co-execution on CPU+GPU

Time series motif (similarities) and discords discovery is one of the most important and challenging problems nowadays for time series analytics. We use an algorithm called “scrimp” that excels in collecting the relevant information of time series by reducing the computational complexity of the searching. Starting from the sequential algorithm we develop parallel alternatives based on a variety of scheduling policies that target different computing devices in a system that integrates a CPU multicore and an embedded GPU. These policies are named Dynamic -using Intel TBB- and Static -using C++11 threads- when targeting the CPU, and they are compared to a heterogeneous adaptive approach named LogFit -using Intel TBB and OpenCL- when targeting the co-execution on the CPU and GPU.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Solving Large-Scale Markov Decision Processes on Low-Power Heterogeneous Platforms

Markov Decision Processes (MDPs) provide a framework for a machine to act autonomously and intelligently in environments where the effects of its actions are not deterministic. MDPs have numerous applications. We focus on practical applications for decision making, such as autonomous driving and service robotics, that have to run on mobile platforms with scarce computing and power resources. In our study, we use Value Iteration to solve MDPs, a core method of the paradigm to find optimal sequences of actions, which is well known for its high computational cost. In order to solve these computationally complex problems efficiently in platforms with stringent power consumption constraints, high-performance accelerator hardware and parallelised software come to the rescue. We introduce a generalisable approach to implement practical applications for decision making, such as autonomous driving on mobile and embedded low-power heterogeneous SoC platforms that integrate an accelerator (GPU) with a multicore. We evaluate three scheduling strategies that enable concurrent execution and efficient use of resources on a variety of SoCs embedding a multicore CPU and integrated GPU, namely Oracle, Dynamic, and LogFit. We compare these strategies for solving an MDP modelling the use-case of autonomous robot navigation in indoor environments on four representative platforms for mobile decision-making applications with a power use ranging from 4 to 65 Watts. We provide a rigorous analysis of the results to better understand their behaviour depending on the MDP size and the computing platform. Our experimental results show that by using CPU-GPU heterogeneous strategies, the computation time and energy required are considerably reduced with respect to multicore implementation, regardless of the computational platform.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech. This work was partially supported by the Spanish project TIN 2016-80920-R

Aplicacions per a un diccionari de gestos base d'un sistema de comunicacions

[ES] Implementación de aplicaciones necesarias para el estudio de un diccionario de gestos genérico que controla los elementos de la interfaz gráfica 3D de terminales de usuario de sistemas de comunicaciones de vídeo con el objetivo de proporcionar mayor sensación de inmersión y mayor accesibilidad a los usuarios mediante gestos que sean naturales.[EN] Implementation of necessary applications to study a generic dictionary of gestures that manages the elements of the 3D graphical user interface in user terminals of video communication systems.The aim is to provide higher immersion sensation and higher accesibility for the users through the most natural gestures.[CA] L¿objectiu d¿aquesta tesina és la implementació de diferents aplicacions necessàries per a l¿estudi prospectiu d¿un diccionari de gestos genèric que controla els elements de la interfaç gràfica de terminals que proporcionen major sensació d¿immersió així com una major accessibilitat als usuaris. La interfaç del terminal d¿usuari d¿un sistema de comunicacions de vídeo de nova generació és gestual i es pretén que els gestos que controlen aquesta interfaç gràfica 3D siguen el més naturals possible. D¿ací va sorgir la idea d¿aquesta tesina. En aquest document s¿explica l¿origen i en què consisteix breument (secció 1), així com el sistema general per al que s¿implementa (secció 2). A continuació es descriu el plantejament inicial de l¿activitat `Interfaç d¿usuari¿ dins d¿aquest context (secció 3) i les diferents parts que la composen, començant amb la interfaç gestual a la secció 4 i seguidament amb la interfaç gràfica a la secció 5. Finalment, es presenten les diferents aplicacions gràfiques que s¿han implementat per a aquest diccionari gestual.Calabuig Navarro, MA. (2009). Aplicacions per a un diccionari de gestos base d'un sistema de comunicacions. http://hdl.handle.net/10251/27342.Archivo delegad

El espinar esclerófilo de Asparago Albi-Rhamnetum "Bethurici" en el subsector Ribaduriense

Se aportan datos ecológicos, florïsticos y fitosociológicos acerca del espinar esclerófilo comprendido en la asociación Asparago albi-Rhamnetum "bethurici" Ladero 1970 del horizonte inferior del piso bioclimático mesomediterráneo seco en el Subsector Ribaduriense (Sector Lusitano-Duriense), límite septentrional de su área.The present work contributes ecological, floristic and phytosociological data about the sclerophilus thombush found in the association Asparago albi-Rhamnetum "bethurici" Ladero 1970 of the lower stratum of dry mesomediterranean bioclimatic level of the Ribaduriense subsector (Lusitano-Duriense sector), the nothermost limit of its area

Memoria Transaccional Software en Procesadores CPU+GPU Heterogéneos

En los procesadores multi-núcleo, la memoria transaccional (TM) ha aparecido como una alternativa prometedora a las técnicas basadas en cerrojos para garantizar exclusión mutua y está siendo incluida como parte de procesadores comerciales. De igual forma, dado que las GPUs se están convirtiendo en el acelerador más popular de la actualidad, los fabricantes están integrándolas dentro del mismo chip, creando las llamadas APUs (Accelerated Processing Units). Sin embargo, la sincronización entre CPU y GPU aún se lleva a cabo con mecanismos muy simples basados en operaciones atómicas y señales. Por tanto, es responsabilidad de los programadores implementar técnicas más avanzadas de exclusión mútua. Las técnicas basadas en TM aún no han sido explotadas en este tipo de procesadores y, por tanto, es importante hacer propuestas de sincronización avanzadas. En este artículo proponemos una librería de TM software enfocada a su uso en procesadores APU. El objetivo es que las transacciones puedan ejecutarse tanto en CPU como en GPU simultáneamente y que se permita la sincronización en forma de exclusión mutua entre ambos dispositivos. Nuestra propuesta, llamada APUTM, se enfoca en minimizar la comunicación entre la CPU y la GPU de los metadatos requeridos para manejar TM. La evaluación de esta propuesta muestra que, utilizando este mecanismo de sincronización, es posible mejorar el tiempo de ejecución de las aplicaciones secuenciales con un reducido esfuerzo en la programación